EDA课程设计——基于VHDL语言的数字时钟设计

d_daout,minute_daout:std_logic_vector(6downto0);signalhour_daout:std_logic_vector(5downto0);signalseltime_daout:std_logic_vector(3downto0);signalledout:std_logic_vector(6downto0);begina<=ledout(6);b<=ledout(5);c<=ledout(4);d<=ledout(3);e<=ledout(2);f<=ledout(1);g<=ledout(0);u1:secondportmap(reset=>reset,clk=>clk,setmin=>setmin,enmin=>enmin_re,daout=>second_daout);u2:minuteportmap(clk=>enmin_re,clk1=>clk,reset=>reset,sethour=>sethour,enhour=>enhour_re,daout=>minute_daout);u3:hourportmap(clk=>enhour_re,reset=>reset,daout=>hour_daout);u4:alertportmap(clk=>clk,dain=>minute_daout,speak=>speaker,lamp=>lamp);u5:seltimeportmap(clk1=>clkdsp,reset=>reset,sec=>second_daout,min=>minute_daout,hour=>hour_daout,daout=>seltime_daout,dp=>dpout,sel=>sel);u6:deledportmap(num=>seltime_daout,led=>ledout);enda;