Рuse ieee.std_logic_1164.all;Рentity bmux isРport(d1,d2:in integer range 0 to 15;Рcs,rst:in std_logic;Рq:out integer range 0 to 15); Рend;Рarchitecture bhv of bmux isРbegin Рprocess(cs,rst)РbeginРif rst='1' then Р q<=0;РelseРcase cs isРwhen '0'=>q<=d1; Рwhen '1'=>q<=d2; Рwhen others=>q<=d1;Рend case;Рend if;Рend process;Рend;Р形成的模块框图为:Р Р图8 选择播放模式和手动模块图Р2.2.3分频模块单元Р本设计中需要的频率12KHz分频到4Hz. Р.分频模块代码为Рlibrary ieee;Рuse ieee.std_logic_1164.all;Рentity fenpin isРport(clk:in std_logic ;Р clkout:buffer std_logic);Рend ;Рarchitecture bhv of fenpin isР---------signal temp:integer range 0 to 3000000;РbeginРprocess(clk)Рvariable temp :integer range 0 to 1500000;РbeginРif clk'event and clk='1' thenРtemp:=temp+1;Рif temp=150 thenРclkout<=not clkout;Рtemp:=0;Рend if;end if;Рend process;Рend bhv;Р分频模块的图如下:
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