基于FPGA的数字时钟课程设计

T3<=23'b0000_0000_0000_0000_0000_000;Р CLK4H<=~CLK4H;Р endР elseР beginР CNT3<=CNT3+1'b1;Р endРendРendmoduleР二、控制模块代码:Рmodule DZZ_T(KEY,RESET,HOUR,MIN,SEC,TS,D,EN,CLK4H);Рoutput?[4:0]HOUR; Рoutput?[5:0]MIN; Рoutput?[5:0]SEC; Рoutput?D; Рoutput?[1:0]TS; Рoutput?EN; Рinput [1:0]KEY; Рinput RESET; Рinput?CLK4H;Рreg [4:0]HOUR;Рreg [5:0]MIN;Рreg [5:0]SEC;Рreg EN;Рreg D;Рreg [1:0]TS;Рalways @(negedge RESET or posedge CLK4H)РbeginР?if(!RESET)Р?beginР HOUR=5'b00000;Р MIN=6'b000000;Р SEC=6'b000000;Р TS=2'b00;Р EN=0;Р D=0;Р?endР?elseР?beginР EN=1;Р if(!KEY[1])Р beginР TS=TS+1'b1;Р endР?elseР?beginР TS=TS;Р?endР?if(!KEY[0])Р?begin Р D=1; //guan jianР EN=1;?Р?endР?elseР?beginР D=0;Р EN=1;Р?endР?endР РendРendmoduleР三、计时调整时间模块代码:Р(1)小时计时和小时计时的调整:Рmodule DZZ_H(DATA_H,HOUR,CLK,D,KEN,TS);Рoutput?[4:0]HOUR;