基于VHDL的数字时钟设计

<=hl;--时个位在数码管7上显示when•’111’’=>xuanze<=M0111111ln;A<=h2;--时十位在数码管8上显示whenothers=>null;endcase;endprocessplO;pil:process(A)begincaseAiswhen”0000"=〉xianshi<=nl1000000”;?--显示0when”0001"=〉xianshi<=•’11111001n;?--显示1when”0010"=〉xianshi<=n10100100n;?--显示2whenn0011”=〉xianshi<=”10110000”;?--显示3when.’0100"=〉xianshi<=”10011001n;?--显示4when”0101"=〉xianshi<=n10010010”;?--显示5when”0110"=〉xianshi<=n10000010”;?--显示6whenn0111”=〉xianshi<=”11111000n;?--显示7whenn1000"=〉xianshi<=n10000000”;?--显示8whenn1001”=〉xianshi<=n10010000”;?--显示9when”1010’’=〉xianshi<=’’10111111’’;?--显示--whenn1011”=>xianshi<=n10111111";?--显示--whenothers=>null;?--数码管的段选设计endcase;endprocesspi1;Pl2:process(xiang)beginifxiang=Tthenbuzzer<=’(T;--当进位信号xiang为1时就把低电平给buzzer让蜂鸣器响elsebuzzer<-T;?--否则把高电平给buzzer不给蜂鸣器触发信号endif;endprocesspi2;?--结束进程endone;