EDA时钟设计报告

';Р elseР alarm_clock<='0';Р end if;Р end if;Рend if;Рend process;Рend bhv;Рlibrary ieee; --时计数VHDL描述Рuse ieee.std_logic_1164.all;Рuse ieee.std_logic_unsigned.all;Рentity hour isР port (h_en,clk,reset:in std_logic;Р hour1,hour2:out std_logic_vector(3 downto 0));Р end hour;Рarchitecture rt1 of hour isР signal hour1_t,hour2_t:std_logic_vector(3 downto 0);РbeginРprocess(clk,reset)РbeginР if h_en='1' thenР if reset='1'thenР hour1_t<="0000";Р hour2_t<="0000";Р elsif clk'event and clk='1'thenР if hour1_t="0011" and hour2_t="0010"thenР hour1_t<="0000";Р hour2_t<="0000";Р elseР if hour1_t="1001"thenР hour1_t<="0000";Р if hour2_t="0010"thenР hour2_t<="0000";Р elseР hour2_t<=hour2_t+1;Р end if;Р elseР hour1_t<=hour1_t+1;Р end if;Р end if;Р end if;Рend if;Рend process;Р hour1<=hour1_t;Рhour2<=hour2_t