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基于VHDL的数字秒表设计

上传者:梦&殇 |  格式:doc  |  页数:12 |  大小:0KB

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ledout( 1 );c => ledout( 2 );d => ledout( 3 );e => ledout( 4 );f => ledout( 5 );g = > ledout( 6 ); u1: count10 port map(clk,stop,start,daout1,count_ cout (0)); u2: count10 port map(count_ cout (0),stop,start,daout2,count_ cout (1)); u3: count10 port map(count_ cout (1),stop,start,daout3,count_ cout (2)); u4: count6 port map(count_ cout (2),stop,start,daout4,count_ cout (3)); u5: count10 port map(count_ cout (3),stop,start,daout5,count_ cout (4)); u6: count6 port map(count_ cout (4),stop,start,daout6,count_ cout (5)); u7:cfq port map(clk2,count_cout(5),count_cout(6)); u7:seltime port map(stop,clk,daout1,daout2,daout3,daout4,daout5,daout6,sel,daout7); u8: ym port map(daout7,ledout); u9: clkgen port map (clk , newclk); end c; 六、程序功能仿真图: 1、 count6 仿真图如下示: 2、 count 10 仿真图如下示: 3、 seltime 仿真图如下示:

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