,clk; Р?output reg clk_1hz,clk_10hz,clk_100hz,clk_1khz;Р?reg [29:0] counter1,counter2,counter3,counter4; //分频计数值Р?always @(posedge clk or negedge reset) Р?beginР if(!reset) Р beginР counter1<=0;counter2<=0;counter3<=0;counter4<=0;Р clk_1hz<=0;clk_10hz<=0;clk_100hz<=0;clk_1khz<=0;Р end?else beginР if(counter1==2400000)Р begin counter1<=0;clk_1hz<=~clk_1hz; endР else begin counter1<=counter1+1; endР if(counter2==240000) begin counter2<=0;clk_10hz<=~clk_10hz;end else Р begin counter2<=counter2+1; endР if(counter3==24000) Р begin counter3<=0;clk_100hz<=~clk_100hz; endР else Р begin counter3<=counter3+1; endР if(counter4==2400) Р begin counter4<=0;clk_1khz<=~clk_1khz; endРelseР begin counter4<=counter4+1; endР end?Р?endР?endmoduleР仿真图如下所示:Р3.2闸门选择器:Р该模块主要实现对闸门的选择功能,通过输入的门选信号来确定输出的闸门,生成的模块如下图所示:
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