毕业论文（设计）基于verilog的数字频率计代码仿真和报告说明书

_100hz;ff<=2'b10;end else if(key1==0&&key10==0&&key100==1) begin gate<=clk_1khz;ff<=2'b11;end else begin ff<=0;end end end //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// always @(posedge gate) begin count<=count+1; if (count<=9) begin gate_out1<=1;clk_clear<=0;clk_latch<=0;end else if (count==11) begin gate_out1<=0;clk_clear<=0;clk_latch<=1;end else if (count==13) begin gate_out1<=0;clk_clear<=1;clk_latch<=0;count<=0;end else begin gate_out1<=0;clk_clear<=0;clk_latch<=0;end end endmodule 仿真图仿真模块三,计数器程序 module counter(rest,start,t6,yichu,clk_clear); input rest,start,clk_in,clk_clear; output yichu; reg yichu; output reg [4:t6; initial begin yichu=1; cnt1<=4't2<=4't3<=4't4<=4'b0000; cnt5<=4'b0000; cnt6<=4'b0000; end