全文预览

基于verilog hdl数字频率计的设计

上传者:upcfxx |  格式:doc  |  页数:40 |  大小:35KB

文档介绍
ecoder的接口电路····················································· 18Р 4.4.2 BCD译码模块dispdecoder的程序设计····················································· 19Р 第5章数字频率计系统的仿真分析··················································································Р 23Р 5.1 系统原理图·············································································································· 23Р 5.2 多路选择模块DATA_MUX的仿真分析······································································· 24Р 5.3 动态位选模块DISPSELEC的仿真分析······································································ 25Р 5.4 BCD译码模块DISPDECODER的仿真分析···································································· 25Р 5.5 软硬件调试··············································································································

收藏

分享

举报
下载此文档