基于Verilog的数字频率计的设计包含代码及仿真

1;clk_latch<=0;count<=0;end else begingate_out1<=0;clk_clear<=0;clk_latch<=0;end?endendmodule仿真图仿真模块三,计数器程序modulecounter(rest,start,t6,yichu,clk_clear);inputrest,start,clk_in,clk_clear;outputyichu;regyichu;outputreg[4:t6; initialbegin?yichu=1; cnt1<=4't2<=4't3<=4't4<=4't5<=4'b0000; cnt6<=4'b0000;endalways@(posedgeclk_in)beginif(!rest)t1<=4't2<=4't3<=4't4<=4't5<=4't6<=4'b0000;endelsebeginif(clk_clear==1)t1<=4't2<=4't3<=4't4<=4't5<=4't6<=4'b0000;yichu<=1;?endelseif(start==1)begin if((cnt6==4'b1001)&&(cnt5==4'b1001)&&(cnt4==4'b1001)&&(cnt3==4'b1001)&&(cnt2==4'b1001)&&(cnt1==4'b1001))t1<=4't2<=4'b0000; cnt3<=4't4<=4't5<=4't6<=4'b0000; yichu<=0; end elseif((cnt5==4'b1001)&&(cnt4==4'b1001)&&(cnt3==4'b1001)&&(cnt2==4'b1001)&&(cnt1==4'b1001))t1<=4't2<=4't3<=4't4<=4'b0000; cnt5<=4't6<=cnt6+4'b0001;