FPGA实验——+8位数码显示频率计设计

begincount<=count+1'b1;endelsebegincount<=1'b0;clk_out<=~clk_out;endendmodulemoduleshili(outputreg[6:0]h1,input[3:0]c,inputclk);always@(c)begincase(c[3:0])4'b0000:h1<='b1000000;4'b0001:h1<='b1111001;4'b0010:h1<='b0100100;4'b0011:h1<='b0110000;4'b0100:h1<='b0011001;4'b0101:h1<='b0010010;4'b0110:h1<='b0000010;4'b0111:h1<='b1111000;4'b1000:h1<='b0000000;4'b1001:h1<='b0010000;4'b1010:h1<='b0001000;4'b1011:h1<='b0000011;4'b1100:h1<='b1000110;4'b1101:h1<='b0100001;4'b1110:h1<='b0000110;4'b1111:h1<='b0001110;default:h1<='b1000000;endcaseendendmodulemoduletop_sevev(output[63:0]H,            //H必须为wire行变量input[31:0]freq,inputclk);shiliseven_0(H[7:0],freq[3:0],clk);       //八个七段数码管的模块的实例化shiliseven_1(H[15:8],freq[7:4],clk);shiliseven_2(H[23:16],freq[11:8],clk);shiliseven_3(H[31:24],freq[15:12],clk);