基于FPGA的七段数码管显示设计

deout,clk);РOutput [6:0] decodeout;Рinput clk;РReg [6:0] decodeout;РWire [3:0] indec;РWire [35:0] control0;РWire [35:0] control1;РWire [35:0] control1;РWire clk;РWire [31:0] date;РWire [1:0] trig0;РWire [1:0] trig1;РWire [6:0] async_in;РWire [3:0] async_out;РAssign trig0=indec [1:0];РAssign trig1=indec [3:2];РAssign async_in=decodeout;РAssign indec=async_out;РAlways @(indec)РBeginРCase(indec)//用case语句进行译码Р4’d0:decodeout=7’b1111110;Р4’d1:decodeout=7’b0110000;Р4’d2:decodeout=7’b1101101;Р4’d3:decodeout=7’b1111001;Р4’d4:decodeout=7’b0110011;Р4’d5:decodeout=7’b1011011;Р4’d6:decodeout=7’b1011111;Р4’d7:decodeout=7’b1111011;РDefault:decodeout=7’bx;РEndcaseРEndРIcon i_iconР ( Р .control0(control0),Р .control1(control1)Р );РIla i_ilaР (Р .control0(control0),Р .clk(clk),Р .date(date),Р .trig0(trig0),