edin any one of them. Three strategies are very useful:Р • Increase the Vgs during ESD, which has been shown to decrease the snapback voltageР [Pol92].Р • Reduce the channel length to decrease the snapback voltage since the β of the npn increasesР due to its smaller base.Р • Add ballast resistance.РThe first strategy is discussedbriefly in Section 3.3.1.3. The second one is intuitivelyclear butРthe latter may require some clarification.Р The influence of adding a drain resistor ballast, or simply ballasting, may beunderstoodbyРexamining a two finger GGNMOS as depictedinFig. 3.11. Fig. 3.11(a) shows thetwofingerРdevice without ballasting. Again , say a positive pulse arrivesatthepad.Thevoltage at thepad,РVpad = Vd1 = Vd2 increases. Now suppose finger 1 goes into snapback first. The voltage over the
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