高精度自动变模控制全数字锁相环研究与设计

t signal can bephasej itter, increasing themodulus K,to improve thenoise immunity ofDPLL,but willlead to greater capture time and narrow capture bandwidth. Add an hange.mode controller totheoriginal all—digitalphase_locked Ⅲ工程硕士学位论文 loop on thebasicprinciple,control on thedigitalloop filtermodulus,to reduce the capture time,a view toincreasing theoperating frequency.This design uses VHDL language toprogram theentire PLL system,functional simulation inModelSim,and achieved theanticipatedrequirements essfully. PLL iswidely used inthediscussion ofthe basis mon applications; thispaper focuses on the design of the new all·-digitalphase··locked loop inthe time-digital convener KeyWords:AllDigital Phase Locked Loop;Automatic Modulus Control;Automatic Hardware language ofVHDL;Capture time;Noise IV