数字逻辑电路实验报告

yieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityalert_06isport(f1,f0,m1,m0:instd_logic_vector(3downto0);siga,sigb:outstd_logic);endalert_06;architectureaofalert_06isbeginsiga<='1'when(f1="0101"andf0="1001"andm1="0101"and(m0="0000"orm0="0010"orm0="0100"orm0="0110"orm0="1000"))else'0';sigb<='1'when(f1="0000"andf0="0000"andm1="0000"andm0="0000")else'0';enda;用VHDL语言写的分频器的源代码如下:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfenpin_06isport(clk:instd_logic;?hz512,hz256,hz64,hz4,hz1:outstd_logic);endfenpin_06;architecturefoffenpin_06is?:std_logic_vector(9downto0);begin?process(clk)?begin?if(clk'eventandclk='1')then?="1111111111")<="0000000000";?<=cc+1;?endif;?endif;?endprocess;?hz512<=cc(0);?hz256<=cc(1);?hz64<=cc(3);?hz4<=cc(7);?hz1<=cc(9);endf;