CD4017中文资料（精选）

5 170 ns РtPLH Р VDD = 15V 70 140 Р VDD = 5V 500 1000 Р Decode Out Lines VDD = 10V 200 400 ns Р VDD = 15V 160 320 Р VDD = 5V 200 360 Р Transition Time Carry Out and Decode Р VDD = 10V 100 180 Р Out Lines tTLH РtTLH, VDD = 15V 80 130 Р ns РtTHL VDD = 5V 100 200 Р tTHL VDD = 10V 50 100 Р VDD = 15V 40 80 Р VDD = 5V Measured with 1.0 2 Р Maximum Clock Frequency 最大时钟频 Respect to РfCL VDD = 10V 2.5 5 MHz Р 率 Carry Р VDD = 15V Output Line 3.0 6 Р VDD = 5V 125 250 РtWL, Minimum Clock Pulse Width 最小时钟脉Р VDD = 10V 45 90 ns РtWH 冲宽度Р VDD = 15V 35 70 Р VDD = 5V 20 РtrCL, Clock Rise and Fall Time 时钟上升和Р VDD = 10V 15 ms РtfCL 下降时间Р VDD = 15V 5РVDD = 5V 120 240 Р Minimum Clock Inhibit Data Setup TimeРtSU VDD = 10V 40 80 ns Р 最小时钟抑制数据设置时间Р VDD = 15V 32 65 Р Average Input Capacitance 平均输入РCIN 5 7.5 pF Р 电容