基于忆阻器的脉冲神经网络硬件加速器架构设计 武长春

tor, which integr ates 24K Р neurons and 192M synapses with 0.75K memristor. We deployed a three -layer fully connected Р network on the accelerator and used it to do the inference task of the MNIST dataset. The result Р shows that the accelerator can achieve 148.2 frames per seco nd and 96.4 percent accuracy under Р the frequency of 50MHz. Р Keywords: Spiking Neural Networks, Resistive Random Access Memory, Processing in Р Memory, Leaky Integrate and Fired Model, Hardware Inference Accelerator Р Р * This work is financially supported by NSFC under project No 92064004. Р 16