xilinx平台实现31条mips指令流水线cpu代码

dРendmoduleРmodule clock(LK, input [31:0] clkscale, output reg clk);Р // CCLK crystal clock oscillator 50 MHzРreg [31:0] clkq = 0; // clock register, initial value of 0Р?Рalways@(LK)Р?beginР clkq=clkq+1; // increment clock registerР if (clkq>=clkscale) // clock scalingР beginР clk=~clk;?// output clockР clkq=0; // reset clock registerР endР endРendmoduleР`timescale 1ns / 1psР//////////////////////////////////////////////////////////////////////////////////Р//control_unitР`include "macro.vh"Рmodule ctrl_unit(clk, rst, if_instr, instr, rsrtequ,Р cu_fwda, cu_fwdb, cu_jmp, cu_jr,cu_jal,cu_branch, cu_regrt, cu_sext,Р cu_wpcir, cu_wreg, cu_m2reg, cu_wmem, cu_aluc, cu_shift, cu_aluimm);Р?Р?input clk;Р?input rst;Р?input [31:0] instr;Р?input [31:0] if_instr;Р?input rsrtequ;Р?Р?output [1:0] cu_fwda;