杭电计组实验10-实现R-I-J型指令的CPU设计实验

b11;endendcaseendendendmodule寄存器堆模块:moduleRegister_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);input[4:0]R_Addr_A;input[4:0]R_Addr_B;input[4:0]W_Addr;inputWrite_Reg;input[31:0]W_Data;inputClk;inputReset;output[31:0]R_Data_A;output[31:0]R_Data_B;reg[31:0]REG_Files[0:31];reg[5:0]i;initial//仿真过程中的初始化beginfor(i=0;i<=31;i=i+1)REG_Files[i]=0;endassignR_Data_A=REG_Files[R_Addr_A];assignR_Data_B=REG_Files[R_Addr_B];always@(posedgeClkorposedgeReset)beginif(Reset)for(i=0;i<=31;i=i+1)REG_Files[i]<=0;elseif(Write_Reg&&W_Addr!=0)REG_Files[W_Addr]<=W_Data;endendmoduleALU运算模块:moduleALU(A,B,F,ALU_OP,ZF,OF);input[31:0]A,B;input[2:0]ALU_OP;outputregZF,OF;outputreg[31:0]F;regC32;always@(*)beginOF=1'b0;C32=1'b0;case(ALU_OP)3'b000:F=A&B;3'b001:F=A|B;3'b010:F=A^B;3'b011:F=~(A^B);