t=data;РendmoduleР顶层模块:Рmodule top(Р clk,rst,data_out,data_in);Р?input clk,rst;Р?output [19:0] data_out;Р?output [15:0] data_in;Р?wire [15:0] data_in;Р?reg [2:0] addra,ct;Р?reg clk1;Р?Р?always@(posedge clk or negedge rst)Р?beginР?if(rst == 0)Р?beginР?ct<=0;Р?clk1<=0;Р?endР?else if(ct==7)Р?beginР?clk1<=~clk1;Р?ct<=0;Р?endР?elseР ct<=ct+1;Р?endР?booth8 U1(Р .data_out(data_out),Р .data_on(data_in)Р );Р Р?rom U2(Р?.clka(clk1), // input clkaР?.addra(addra), // input [2 : 0] addraР?.douta(data_in) // output [15 : 0] doutaР?);Р?Р?always@(posedge clk1 or negedge rst)Р?beginР?if (rst==0)Р?addra <= 0;Р?elseР?addra <= addra + 1;Р?endРendmoduleР测试模块:Рmodule test;Р?// InputsР?reg clk;Р?reg rst;Р?// OutputsР?wire [19:0] data_out;Р?wire [15:0] data_in;Р?// Instantiate the Unit Under Test (UUT)Р?top uut (
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