数字电路实验报告交通灯控制器(VHDL)

ent fenpin is --主分频模块РportР(Р clk:in std_logic;Р clk_out:out std_logic);Рponent;Рcomponent showfenpin is --为数码管共阴极扫描提供扫描频率的分频模块РportР(Р clk:in std_logic;Р clk_out:out std_logic);Рponent;Рcomponent control is --控制器模块Рport(clk:in std_logic;Р emergency:in std_logic;Р reset:in std_logic;Р light1:out std_logic_vector(2 downto 0);Р light2:out std_logic_vector(2 downto 0);Р counter1,counter2:out std_logic_vector(5 downto 0));Рponent;Рcomponent countdown is --计数器模块Рport(clk:in std_logic;Р cat_tmp:out std_logic_vector(5 downto 0);Р numin:out std_logic_vector(3 downto 0); Р emergency:in std_logic;Р reset:in std_logic;Р counter1,counter2:in std_logic_vector(5 downto 0));Рponent;Рcomponent show is --数码管显示译码模块РportР(num_in:in std_logic_vector(3 downto 0);Р num:out std_logic_vector(7 downto 0));Рponent;