CPLD设计BCD的优先编码器BCD码十进制加法计数器8位的左右移位寄存器电路时钟分配电路步进马达控制电路

t3=> F<="001000";Р next_state<=st4; Р when st4=> F<="000100";Р next_state<=st5; Р when st5=> F<="000100";Р next_state<=st6;Р when st6=> F<="000010";Р next_state<=st7; Р when st7=> F<="000001";Р next_state<=st8;Р when st8=> F<="000001";Р next_state<=st0; Р end case;Р?end process;?Р end divide_arch;Р3 时序仿真结果Р4 时序分析Р================================================================================РTiming constraint: Default period analysisР 36 items analyzed, 0 timing errors detected.Р Minimum period is 4.236ns.Р Maximum delay is 10.437ns.Р================================================================================РTiming constraint: enumerationР 14 items analyzed, 0 timing errors detected.Р delay is 2.386ns.Р--------------------------------------------------------------------------------