ndР?else beginР rx_int0 <= rx_int;Р rx_int1 <= rx_int0;Р rx_int2 <= rx_int1;Р endРEndРassign neg_rx_int = ~rx_int1 & rx_int2;?//捕捉到下降沿后,neg_rx_int拉高保持一个主时钟周期Рreg[7:0] tx_data;?//待发送数据的寄存器Рreg bps_start_r;Рreg tx_en;?//发送数据使能信号,高有效Рreg[3:0] num;Рalways @ (posedge clk or negedge rst_n) beginР?if(!rst_n) beginР bps_start_r <= 1'bz;Р tx_en <= 1'b0;Р tx_data <= 8'd0;Р endР?else if(neg_rx_int) begin?//接收数据完毕,准备把接收到的数据发回去Р bps_start_r <= 1'b1;Р tx_data <= rx_data;?//把接收到的数据存入发送数据寄存器Р tx_en <= 1'b1; //进入发送数据状态中Р endР?else if(num==4'd11) begin?//数据发送完成,复位Р bps_start_r <= 1'b0;Р tx_en <= 1'b0;Р endРendРassign bps_start = bps_start_r;Рreg rs232_tx_r;Рreg led1_r;Рalways @ (posedge clk or negedge rst_n) beginР?if(!rst_n) beginР num <= 4'd0;Р rs232_tx_r <= 1'b1;Р led1_r<=1'b0;Р endР?else if(tx_en) begin
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