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(参考)verilog硬件描述语言课程设计

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: romout = 255; 2: romout = 255; 3: romout = 255; 4: romout = 128; 5: romout = 128; 6: romout = 128; 7: romout = 128; 8: romout = 64; 9: romout = 64; 10: romout = 64; 11: romout = 64; 9 12: romout = 0; 13: romout = 0; 14: romout = 0; 15: romout = 0; 16: romout = 255; // 方波初值 17: romout = 255; 18: romout = 255; 19: romout = 255; 20: romout = 255; 21: romout = 255; 22: romout = 255; 23: romout = 255; 24: romout = 0; 25: romout = 0; 26: romout = 0; 27: romout = 0; 28: romout = 0; 29: romout = 0; 30: romout = 0; 31: romout = 0; default : romout = 10'hxx; 10 endcase endfunction always@(posedge f_out) begin if(addr==16) // 波形数据切换 addr=0; else addr=addr+1; case(choose) // 波形选择开关设定 0: address=addr; 1: address=addr+16; endcase end assign data = romout(address);// 将 ROM 中对应数据传递输出端口 data 输出 endmodule

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