lk_out;reg[31:t;always@(posedgeclk_in)beginif(!rst)t<=0;clk_out<=0;t==10000000)//设计分频为1Hz,t<=0;clk_out<=!clk_out;t<=cnt+1;clk_out<=clk_out;endendendmodule2.2.计时模块计时模块如下图所示。图4计时模块//比赛时间倒计时模块,每节12min,共4节modulejishi(clk_1hz,clr,pause,min_out,miao_out,jie);inputclk_1hz;inputclr,pause;output[7:0]min_out,miao_out;output[3:0]jie;reg[7:0]min_out,miao_out;学生:苗茂宇学号:14082020078reg[3:0]jie;;always@(posedgeclk_1hzornegedgeclr)beginif(!clr)beginmin_out<=8'd0;miao_out<=8'd0;endelseif(!pause)beginif(miao_out==8'd0)beginmiao_out<=8'd59;if(min_out==8'd00)beginmin_out<=8'<=1;endelsemin_out<=min_out-8'd1;endelsebeginmiao_out<=miao_out-8'<=0;endendendalways@(ornegedgeclr)beginif(!clr)beginjie<=4'd0;endelsejie<=jie+1'd1;endendmodule计时模块采用倒计时法,其仿真波形如下图所示。1、计时开始,节数为1,分钟位为11,秒位为59,倒计时开始。图5计时开始2、暂停时,给出pause信号,计时暂停。
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