VHDL课程设计-计算器模块设计

ieee.std_logic_1164.all;Рuse ieee.std_logic_arith.all;Рuse ieee.std_logic_unsigned.all;Рentity add isР port(clk :in std_logic;Р reset:in std_logic;Р data:in std_logic_vector(27 downto 0);Р data_pn:in std_logic;Р dout :out std_logic_vector(27 downto 0);Р dout_pn:out std_logicР );Рend entity add;Рarchitecture behave of add is Рsignal temp: std_logic_vector(27 downto 0):="";Рsignal temp_pn:std_logic:='0';РbeginРdout<=temp;Рdout_pn<=temp_pn;Рprocess(clk,reset)РbeginРif(reset='1')then temp<="";temp_pn<='0';Рelsif(clk'event and clk='1')thenР if(temp_pn='0')thenР if(data_pn='0')then temp<=temp+data;temp_pn<='0';Р else Р if(temp>data or temp=data)then temp<=temp-data;temp_pn<='0';Р else temp<=data-temp;temp_pn<='1'; Р end if;Р end if;Р else Р if(data_pn='1')then temp<=temp+data;temp_pn<='1';Р else