浙工大现代交换原理实验报告

uded are auto-zero circuitry and panding coder which samples the filtered signal and encodes it in panded m-law or A-law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from panded m-law or A-law code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks, which may vary from 64 kHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data patible with both industry standard formats。