扩展命题Р5.4 程序设计:Рlibrary ieee;Рuse ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity SCAN_LED is port(clk:in std_logic; end;Рarchitecture one of SCAN_LED is signal cnt8:std_logic_vector(2 downto 0); signal a:integer range 0 to 15; beginРp1:process(cnt8)--段选 beginРcase cnt8 isРwhen \显示1 when \显示3 when \when \when \when \when \when \when others => NULL;Рsg:out std_logic_vector(6 downto 0);--段选信号 bt:out std_logic_vector(7 downto 0));--位选信号РРРРРРРРРРРРРРend case;Р end process p1; p2:process(clk) begin Рif clk'EVENT and clk='1' then cnt8 sg SG SG SG SG SG SG SG SG SG SG SG SG SG SG NULL;Рend case;Р end process p3; end; Р5.5仿真波形:Р Р六、试验思索题Р〔1〕思索如何实现计数器与译码器连接以及不同字母显示电路的设计?Р设计计数器模块和译码器模块,通过模块调用,端口映射,将计数结果输送Р到译码器的输入端口进展译码。РРРР本文来源:网络收集与整理,如有侵权,请联系作者删除,谢谢!