基于verilog hdl的万年历

or negedge clrn)Р beginР if (~clrn) qy=1;Рelse beginРif (qy==’h12) qy=1;Рelse qy=qy+1;Рif (qy[3:0]==’ha) beginРqy[3:0]=0; qy[7:4]=qy[7:4]+1;endРif (qy==’h12) clkn=1;Рelse clkn=1; endРendР//产生每月的天数РalwaysРbeginР case(qy)Р’h01: date=’h31;Р’h01: beginР if((qn/4==0)&( qn/100!==0)|( qn/400==0)) date=’h29; //整百的年份被400整除的,是闰年,其他如果不是整百的年份,直接被4整除的是闰年。Р else date=’h28; endР’h03: date=’h31;Р’h04: date=’h30;Р’h05: date=’h31;Р’h06: date=’h30;Р’h07: date=’h31;Р’h08: date=’h31;Р’h09: date=’h30;Р’h10: date=’h31;Р’h011: date=’h30;Р’h12: date=’h31;Рdefault: date=’h30;РendcaseРendР//年计数模块Рalways@(posedge clkn or negedge clrn)Р beginР if (~clrn) qn[3:0]=0;Рelse begin if (qn[3:0]==9) qn[3:0]=0;Рelse qn[3:0]= qn[3:0]+1;Рif (qn[3:0]==9) clkn1=0;Рelse clkn1=1; endРendРalways@(posedge clkn1 or negedge clrn)Р begin