基于FPGA8位加法器技术

"0000010"; WHEN 7=>LED7S1(20 DOWNTO 14)<="1111000"; WHEN 8=>LED7S1(20 DOWNTO 14)<="0000000"; WHEN 9=>LED7S1(20 DOWNTO 14)<="0010000"; WHEN OTHERS=>LED7S1(20 DOWNTO 14)<="XXXXXXX"; END CASE; END PROCESS; .页眉. . 页脚. PROCESS(CLK3) VARIABLE X: STD_LOGIC_VECTOR(2 DOWNTO 0); --定义一个常量,用来控制位选。 BEGIN IF CLK3'EVENT AND CLK3='1' THEN IF X<5 THEN X:=x+1; ELSE X:=(OTHERS=>'0'); END IF; END IF; XI<=X; END PROCESS; PROCESS(XI,LED7S1) BEGIN CASE XI IS WHEN "001"=>LED7S1<=LED7S1(6 DOWNTO 0);SMG<="100"; WHEN "010"=>LED7S1<=LED7S1(13 DOWNTO 7);SMG<="010"; WHEN "100"=>LED7S1<=LED7S1(20 DOWNTO 14);SMG<="001"; WHEN OTHERS=>LED7S1<="XXXXXXX";SMG<="XXX"; END CASE; END PROCESS; END ARCHITECTURE ONE; 4.2 二进制转十进制显示模块波形输入 8位二进制及进位位时,输出个位、十位、百位波形如图 5所示,由图可知 ModelSim 仿真结果与理论实际相符。图5二进制转十进制显示模块波形图动态显示模块的设计 5.1 动态显示的模块的实现