设计分频器实现:输入时钟频率为50MHZ,输出400HZ、100HZ、25HZ、1HZ时钟module div(clk_50MHz,clk_400Hz,clk_100Hz,clk_25Hz,clk_1Hz);input clk_50MHz;output clk_400Hz,clk_100Hz,clk_25Hz,clk_1Hz;reg clk_400Hz,clk_100Hz,clk_25Hz,clk_1Hz;reg [15:0] cnt1;always@(posedge clk_50MHz)t1==16'd62499) begin cnt1<=0; clk_400Hz<=~clk_400Hz; endelse cnt1<=cnt11'b1;reg [1:0] cnt2;always@(posedge clk_400Hz)t2==1'b1) begin cnt2<=0; clk_100Hz<=~clk_100Hz; endelse cnt2<=cnt21'b1;reg [1:0] cnt3;always@(posedge clk_100Hz)t3==1'b1) begin cnt3<=0; clk_25Hz<=~clk_25Hz; endelse cnt3<=cnt31'b1;reg [5:0] cnt4;always@(posedge clk_100Hz)t4==6'd49) begin cnt4<=0; clk_1Hz<=~clk_1Hz; endelse cnt4<=cnt41'b1;endmodule