基于vhdl语言的智能空调控制器的设计说明书

---clk 时钟 en 开关/使能端Р shiwei,gewei,romeshi,romege: in std_logic_vector(0 to 3); Р ---shiwei 设置温度的十位;Р gewei 设置温度的个位;Р romeshi 设置室温的十位; Р romege 设置温度的个位。Р shiout,geout:out std_logic_vector(0 to 3));Р --- shiout输出温度的十位 geout输出温度的个位Рend wendu;Рarchitecture behave of wendu isРsignal hs,hg:std_logic_vector(0 to 3);РbeginРprocess(clk,en,shiwei,gewei,romeshi,romege,hs,hg)РbeginРif en='0' then Рhs<=romeshi;hg<=romege;Рelsif clk'event and clk='1' thenРif hs&hg<shiwei&gewei then ---室温低于设置的温度,温度上升Рif hg<"1001" then hg<=hg+1;Рelse hg<="0000";hs<=hs+1;Рend if;Рelsif hs&hg>shiwei&gewei then ---室温高于设置的温度,温度下降Рif hg>"0000" then hg<=hg-1;Рelse hg<="1001";hs<=hs-1;Рend if;Рelse hs<=shiwei;hg<=gewei; Р ---判断温度上升或下降到设置的温度,保持温度显示不变Рend if;Рend if;Рshiout<=hs and en&en&en&en;geout<=hg and en&en&en&en; Р ---输出温度