ing this mode. The idle mode can be terminated by any enabled interrupt orbya hardware reset. Note that when idle mode is terminated bya hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins isnot inhibited. To eliminate the possibility of an unexpected write toa port pin when idle mode is terminated bya reset, the instruction following the one that invokes idle mode should not write toa port pin or to external memory. 十四、 Power-down Mode In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special
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