.PLC?¡¢£¤
&'[J].?¥\r¦,2017(07):147-148.\r[4]{§¨.;ZFPGA?©_
&'[J]?ª,2016(01):47.\r[5]«¬v}®.FPGA?
&'?[J].¯°±²³´0\r,2015,18(02):264-265.\r[6]µ¶·¸§¹º»¼,½¾¿.VHDL?¡¢
&'?À.?\r¥¦,2014(35):108-109.\r[7]uÁ4ÂÃÄIJ,º[źƨ.FPGA?
&'[J].Ç?\r,2013,37(01):152-154.\r[8]ÈÉ°.FPGAC
&'??0\n[J].Ê˯´0\n,2011,30(24):15-17.\r[9]ÌÍÎÏÐ.
&'?FPGA´[J].ÑÒR(\r),2011,33(06):82-85.\r[10]«lÓ8,ÔÕÖ×ØÙ.FPGA?
&'?[J].?Ú\rÛ,2011(26):38.\r[11]ÜÝÞ.FPGA?©_
&'[D].ßà)FR,2014.\r[12]áâãäåæçßè.FPGA?éê
&'[J].ëìF\rp?Rí,2007(2):242-244.\r[13]BergeronJ,EbraryI.Writingtestbenches:functionalverificationofHDL\rmodels[J],HumanReproduction,2003,27(6):1668-1675.\r[14]ºÐ/.
&£=[D].ÖîR2014.\r[15]ïð¨.VHDLÑ¢
&'?[J].ñ?,2009,46(01):26-28.\r41