s@(cur_state)\rcase(cur_state)\rsiif(in)next_state<=s2;flag_out<=0;\relsenext_state<=sl;flg_out<=0;\rs2if(in)next_state<=s3;flag_out<=0;\relsenext_state<=sl;flg_out<=0;\rs3if(!in)next_state<=sl;flag_out<=l;\relsenext_state<=sl;flg_out<=0;\rendcaseEvaluationWarning:ThedocumentwascreatedwithSpire.PDFfor.NET.\rendmodule\r15.VerilogHDL\n\rmoduledtrigger(clclkoutl);\r99\rinputclclk;\r9\routputoutl;\rregd9q9out;\ralways@(clk)\rbegin\rd<=-(cllq);\rif(clk==0)\rq<=dp\rout<=-q;\rend\rassignoutl=out;\rendmodule\r16.Verilog\n\rmoduletrig(xinclkyout);\r99\rinputxinclk;\r9\routputyout;\rregdl,d2,ql,q2;\ralways®(clk)\rbeginEvaluationWarning:ThedocumentwascreatedwithSpire.PDFfor.NET.\rdl<=q2;\rd2<=xinlql;\rif(clk==l)\rql<=dl;\rend\ralways@(posedgeelk)\rbegin\rq2<=d2;\rend\rassignyout=q2;\rendmodule
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