AD转换电路的设计与实现

11";РWHEN"1111"=>DX<="1111111111111111";РWHENOTHERS=>NULL;РENDCASE;РENDPROCESS;РEndADC0809;Р2.Рlibraryieee;РUseieee.std_logic_1164.all;РUseieee.std_logic_unsigned.all;РРuseieee.std_logic_arith.all;РEntityzjf2isРPort(clk,int:instd_logic;Рdata:instd_logic_vector(7downto0);CS,WR,RD:outstd_logic;РWX:outstd_logic_vector(3downto0);DX:outstd_logic_vector(15downto0));Endentityzjf2;РArchitectureADC0809ofzjf2isРTypestateis(st0,st1,st2,st3,st4,st5,st6);РSignalcurrent_state,next_state:state:=st0;РSignalzj:std_logic_vector(7downto0);РSignalQH:std_logic_vector(3downto0);РSignalQL:std_logic_vector(3downto0);РSignalshu2:std_logic_vector(3downto0);РSignallock:std_logic;РSignalshu1:std_logic_vector(3downto0);РBeginРProcess(clk)РBeginРif(clk'eventandclk='1')thencurrent_state<=next_state;Рshu1<=shu1-1;РEndif;