ication, we are ready to move into the "back-end" stage The nature of and tools for this stage vary somewhat, depending on the target technology for the design, but there are three basic steps. The first is synthesis, converting the VHDL description into a set of primitives ponents that call be assembled in the target technology. For example, with PLD or CPLD, the synthesis tool may generate two-level sum-of-products equations .With ASIC, it may generate a Iist of gates and list that specifies how they should be interconnected. The designer may "help" the synthesis tool by specif y ing certain technology-specific constraints, such as the max i mum number of logic levels or the strength of logic buffers to use. In the fitting step, a fitting tool or fitter maps the synthesized primitives or
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